A memory system may include a controller and a memory module arranged on a main board. The controller and the memory module may receive and transmit data through data lines arranged adjacent to each other on the main board. A data transmission speed of a case in which identical pieces of data are transmitted through the data lines arranged adjacent to each other (in an even mode) may be decreased more than that of a case in which different pieces of data are transmitted through the data lines (in an odd mode). Accordingly, a data transmission speed difference may occur between the data transmitted through the data lines, and thus signal integrity may be degraded.